1. Field of the Invention
The present invention relates to a semiconductor device which utilizes a crystalline silicon layer as an active layer, and a production method thereof.
2. Description of the Related Art
There is conventionally known an active matrix type display device, which utilizes thin film semiconductors to drive pixels. A typical example of the thin film semiconductor utilized in such a display device includes a thin film silicon semiconductor. The thin film silicon semiconductor is roughly divided into the one formed of an amorphous silicon film and the other formed of a crystalline silicon film.
A thin film transistor which utilizes a crystalline silicon layer as an active layer (crystalline silicon TFT) is larger in mobility than a thin film transistor which utilizes an amorphous silicon layer as an active layer (amorphous silicon TFT), and hence the crystalline silicon TFT has characteristics of high driving performance superior to the amorphous silicon TFT. In addition, as compared with the amorphous silicon TFT, the crystalline silicon TFT has high current stress resistance, and hence has an advantage that a threshold voltage Vth is less shifted after long time driving. Furthermore, of the crystalline silicon TFTs, reduced production cost may be achieved in a crystalline silicon TFT including an active layer which may be formed without the need for a laser annealing process or ion doping process for crystallization, as compared with a case of including an active layer of low-temperature polycrystalline silicon. Still further, such crystalline silicon TFT does not suffer from a variation in crystallinity caused by the laser annealing process, and hence has another advantage of being formed over a large area with ease.
However, the crystalline silicon TFT suffers from a problem of increased off-state leakage current, and hence various measures against the problem have been provided.
Japanese Patent Application Laid-Open No. 2001-077372 proposes a top-gate staggered TFT having a stacked structure of an amorphous silicon layer and a polycrystalline silicon layer formed on the amorphous silicon layer, which serve as a semiconductor layer on source and drain electrodes. The amorphous silicon layer is formed on n+ Si layers of the source electrode and the drain electrode, and positioned at an interface of a channel on an opposite side thereof. As proposed in Japanese Patent Application Laid-Open No. 2001-077372, the amorphous silicon layer, which has a wide band gap, is deposited on the n+ Si layers at a prescribed film thickness or more, to thereby reduce off-state leakage current flowing through a back channel of an active layer.
However, in the structure proposed in Japanese Patent Application Laid-Open No. 2001-077372, a heterojunction is formed between the active layer having a narrow band gap and the amorphous silicon layer having a wide band gap. When electrons flow into the drain electrode, a potential barrier formed at the heterojunction portion hinders the electrons from flowing in a reverse direction from the active layer into the amorphous silicon layer. If an electric field between the source and the drain is small, electrons are less likely to flow therebetween due to the barrier, which arises a problem that current rising characteristics are deteriorated.
In order to exhibit the characteristics inherent in the crystalline silicon semiconductor device sufficiently enough to be put into practical use, off-state leakage current needs to be suppressed without deteriorating the rising characteristics of current between the source electrode and the drain electrode.